Many modern integrated circuits are complicated arrangements of millions of individual elements called Metal-Oxide-Semiconductor Field-Effect Transistors (“MOSFETs”). The remarkable decades-long progression in the performance of state-of-the-art electronics has been enabled by steadily shrinking the size of these transistors. The desired pace of MOSFET device scaling has the gate-length (i.e., size) of transistors shrinking to less than 100 nanometers (nm). But achieving this size scale is problematic. In particular, for transistors formed using conventional bulk silicon substrates, performance begins to suffer when gate length is reduced to less than 100 nm. At this size scale, substrate effects and physical limitations associated with silicon dioxide gate dielectric material become severe.
To meet this challenge, new material systems and transistor structures are being considered. Three technologies that have attracted the interest of researchers are:                Fully-depleted silicon-on-insulator technology;        dual-gate transistor technology; and        High-K dielectric materials.These technologies, and their limitations for use in very short gate-length transistors, are discussed in some detail below.        
Silicon-on-insulator (SOI) technology was introduced to overcome some of the limitations on transistor scaling associated with the use of a bulk silicon wafer. An SOI substrate comprises a silicon active layer that is separated from a bulk silicon handle wafer by a buried silicon dioxide layer. Transistors, such as MOSFETs, are formed in the active layer. Many deleterious substrate effects are mitigated by the fact that the transistors are formed in a layer that is insulated from the substrate.
A conventional MOSFET has four electrical terminals, drain, source, gate, and substrate. Structurally, the gate comprises an electrically-conductive polysilicon layer (i.e., a gate conductor) that is disposed on a silicon dioxide layer (i.e., a gate dielectric). The gate dielectric electrically isolates the gate conductor from the active layer, and acts as one plate of a capacitor structure. The region of the active layer that is located directly under the gate is called the channel. Typically, the channel is doped so that it contains either negative charge carriers (electrons) or positive charge carriers (holes). The channel is bracketed by a source and a drain, which are typically doped with a charge carrier opposite to those in the channel. The gate, gate dielectric, and channel reside on substantially parallel planes, and these transistors are referred to as “planar single gate” MOSFETs.
When a voltage is applied to the gate terminal, an electric field is created under the gate, which drives away existing charge carriers in channel. This creates a charge carrier “depletion region” in the channel. For a gate voltage that is sufficiently high (i.e., greater than a “threshold voltage”), a carrier-type “inversion” occurs in the channel and electric current can flow between the source and drain. In other words, the MOSFET is activated by the application of a gate voltage higher than the threshold voltage.
MOSFET transistors having gate lengths greater than 50 to 65 nm typically operate in what is referred to as “partial depletion” mode. In partial depletion mode transistors (PD-SOI), the active layer thickness is typically greater than 200 nm. During operation, the depletion region extends only partly into the active layer (i.e., it is partially-depleted). For transistors having gate-lengths shorter than 50 nm, however, PD-SOI transistor operation suffers from severe short-channel effects and exhibits a poor on/off current ratio.
Full-depletion mode transistor technology (FD-SOI) mitigates some of the problems faced by PD-SOI. FD-SOI is characterized by an active layer that is extremely thin (typically <70 nm). The active layer is thin enough, in fact, that the depletion region extends through the entire thickness of the active layer (i.e., the active layer is “fully-depleted”). As a result, short-channel effects are less severe and transistor operation is improved over PD-SOI.
For transistors having gate-lengths as small as 15-20 nm, however, it is expected that even FD-SOI planar single gate transistor technology will not suffice due to the effects from substrate interactions. Exotic, non-planar transistor technologies, therefore, are being considered. These include vertical double or triple gate MOSFET structures. In these vertical structures, the active layer comprises a “fin” that projects up from the substrate surface. A gate is formed on either side of this fin to form a double-gate transistor. This structure is sometimes referred to as a “FINFET.” A triple-gate transistor is formed by an active layer fin having gates formed on both sides and the top. The attraction for these multi-gate devices lies in significantly improved electrostatic integrity and transistor operation.
While multi-gate transistors are attractive for their operational characteristics, the fabrication complexity for vertical gate transistors represents a significant barrier to their wide-spread use. To date, the integrated circuit industry has been focused primarily upon planar processing technology. Vertical structures (and associated fabrication processes) represent a significant departure from proven technologies. Their fabrication processes are more complex than those used to fabricate planar devices. As a result, manufacturing of vertically-oriented multi-gate transistors is much costlier. In addition, device and circuit designs for vertical transistors are unproven. Finally, orientation of the fin structure with respect to active layer's crystal structure affects the speed at which the charge carriers travel in the vertical active layer. This fact makes circuit layout for vertical transistors much more complicated than for more conventional devices.
As the gate length of the transistor scales below 100 nm, the thickness of the conventional silicon dioxide gate dielectric becomes extremely thin (approximately 2 nm). At this thickness, silicon dioxide no longer provides sufficient electrical isolation. Direct carrier tunneling through these thin oxides increases transistor leakage current and, therefore, integrated circuit power dissipation.
Materials that have a relatively high dielectric constant—so called “high-K dielectrics”—might provide some advantage as a gate dielectric. High-K dielectric materials are therefore being developed in order to replace silicon dioxide in short gate-length transistors (<100 nm). Examples of high-K dielectrics under investigation include hafnium oxide and silicon oxynitride. To the extent that these materials have a higher dielectric constant than silicon dioxide, the same operational characteristics as thin silicon dioxides can be derived with thicker high-K dielectric layers. Alternatively, thin high-K gate dielectrics used in place of thin silicon dioxide gate dielectrics enable transistor operation at lower gate voltage, thereby reducing gate leakage current, etc. To date, however, material quality, morphology issues, and poor interface quality have limited the benefits of high-K dielectric materials vis-à-vis their use as gate dielectrics.
Charge-carrier tunneling through thin silicon dioxide gate dielectrics can also arise due to dopant poisoning of the transistor. Such poisoning can occur during fabrication, as explained below. In typical, conventional SOI-based transistors, the gate conductor is polysilicon. The polysilicon must be doped (typically with boron) in order to make it sufficiently conductive. Once present in the polysilicon, the dopant must be activated by means of a high-temperature anneal. At elevated temperatures, the diffusivity of boron along the grain boundaries of the polysilicon, and through silicon dioxide, is quite high. As a consequence, when subjected to the elevated annealing temperatures, boron can penetrate the gate oxide and enter the channel underneath, thereby poisoning the transistors.
A transistor technology that mitigates at least some of the costs and disadvantages of the prior-art, therefore, would be a significant advance in the state-of-the-art of microelectronics.